1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which can make writing more speedy; and a layout structure thereof.
2. Description of the Related Art
FIG. 1 is a block view illustrating a layout structure of a semiconductor memory device as prior art. As shown in FIG. 1, the memory device has a memory cell array area 1 having a great number of memory cells MC arranged in a matrix form. The end portion of the memory cell array area 1 has a dummy cell area 2, in which memory cells DMC having a purpose different from the purpose that actual information is stored are arranged. The memory cells DMC are memory cells having the same shape as internal memory cells MC which are arranged outside the memory cells for storing information and have a purpose different from that of a functional operation, these internal cells being arranged for measuring a specific nature of a finished layout or electric performance of the memory cells which is caused by existence of a one-side pattern. Word lines WL0-WLp which show line addresses are gate wirings of transistors (not shown) which constitute the memory cells MC. As a material thereof, polysilicone is used. In order to restrain delay in the words lines WL0-WLp, wirings 5 made of a low resistance metal such aluminum or tungsten run in parallel to and over the word lines WL0-WLp. The wirings 5 and the word lines are connected to each other at regular intervals by means of liners (CT). For this purpose, the memory cell array area 1 has word line-suspending sections 3 for the connection by the lines. At the portions of a sense amplifier area 4 which correspond to the dummy cell area 2 and the word line-suspending sections 3, no sense amplifier is necessary from the viewpoint of operation. However, sense amplifiers DSAa, DSAb having a purpose different from functional operation are arranged to avoid a disturbance of repetition of pattern in the same way as the dummy cell area 2 is arranged in the memory cell area 1. The word lines WL0-WLp are connected to memory cells MC necessary for operation along the line direction, and one of the word lines is selected in operation. Along the row direction, to each pair of bit lines to which memory cells are connected, i.e., each of (BL0/BLB0)-(BLm/BLBm), connected is either one of sense amplifiers SA0-SAm for detecting the potential difference between the pair of each of the bit lines (BL0/BLB0)-(BLm/BLBm), and amplifying the potential difference to a predetermined value. Each of the pairs of bit lines (BL0/BLB0)-(BLm/BLBm) has either one of separation controlling gates SW0-SWm for controlling connection with and separation from a pair of data path lines (DB/DBB). Each of the pairs of bit lines (BL0/BLB0)-(BLm/BLBm) is connected to and separated from the pair of data path lines DB/DBB by the row address signals YS0-YSm. A write amplifier WA is activated by a write controlling signal WENA so that a write data signal WDATA taken in from the outside is driven to the pair of data path lines DB/DBB, as complementary data.
In the same manner as in the internal memory cells MC, to the memory cells DMC in the dummy cell area 2, connected are the word lines WL0-WLp, and the information in the memory cells DMC which is selected through the word lines WL0-WLp is read by a pair of bit lines BLa/BLBa connected thereto. The sense amplifier DSAa is connected to the pair of bit lines BLa/BLBa. The pairs of bit lines BLa/BLBa and those of bit lines BLb/BLBb, which are inputs into and outputs from the sense amplifiers DSAa and DSAb, have a separation controlling gate SWa or SWb which is the same as the separation controlling gates SW0-SWm; however, the row address signals YS0-YSm are not inputted into the pairs of bit lines BLa/BLBa and those of bit lines BLb/BLBb. The inputs are earth-connected. Thus, the data path lines DB/DBB are separated from the pairs of bit lines BLa/BLBa and those of bit lines BLb/BLBb so that the memory cells DMC are not concerned with functional operation.
The following will describe operation of the semiconductor memory device as prior art, referring to FIGS. 2 and 3. FIG. 2 shows operation timing of writing, and FIG. 3 is a timing chart showing operation timing of block write.
Firstly, one of the word lines WL0-WLp is selected to be turned into a H level (it is presumed that the word line WL0 is selected). The information which the memory cell DMC and memory cells MC to which the word line WL0 is connected store is read by BLa and one-side pieces BL0-BLm of the respective pairs of bit lines to which the memory cells MC and memory cells DMC are connected, which are beforehand set to a recharge voltage HVDD and then are fallen into a floating state. The voltages of the read bit lines BL0-BLm and BLa become the potential differences between the pair of bit lines, respectively. When the sense amplifier SA0-SAm and SAa are activated, the potential differences cause the pair of bit lines (BL0/BLB0)-(BLm/BLBm) and that of bit lines BLa/BLBa to be amplified to predetermined levels.
When the write controlling signal WENA is turned into a H level, the write amplifier WA drives the write data signal WDATA into the pair of data path lines DB/DBB as complementary data. After or before this, one of row address signals YS0-YSm is selected (it is presumed that the row address signal YS0 is selected.). As a result, the row address signal YS0 is turned to a H level to select the separation controlling gate SW0. Thus, the pair of data path lines DB/DBB and the pair of bit lines BL0/BLB0 are connected to each other, and by the write amplifier WA write data are set into the sense amplifier SA0, so that the write data are written in the memory cell MC at which the word line WL0 crosses the pair of bit lines BL0/BLB0. After that, the level of the word line WL0 is dropped to finish writing operation.
The semiconductor memory device used for image processing and the like (such as VRAM, GRAM or SGRAM) may have a block write function of selecting plural row address signals YS0-YSm at the same time and carrying out writing into plural memory cells MC at the same time. During a series of the writing process, in the dummy cell area 2, DSAa is also operated in the same manner as the internal sense amplifiers SA0 and SAm so that the noise property of the sense amplifier SA0 does not have a specific nature. Specifically, the word lines WL0-WLm are also connected to the memory cells DMC, and when, for example, the word line WL0 rises correspondingly to the aforementioned operation example, the information in the memory cell DMC connected thereto is read. When the sense amplifier DSAa is activated, the potential difference between the pair of bit lines BLa/BLBa causes the pair of the bit lines BLa/BLBa to be amplified to a predetermined level. However, the input of the separation controlling gate SWa is earth-connected, and consequently the information in the pair of bit lines BLa/BLBa is not transmitted to the pair of data path lines DB/DBB nor the information in the pair of data path lines DB/DBB is not transmitted to the pair of bit lines BLa/BLBa reversibly.
The sense amplifier DSAb has a purpose for reducing property-dependency on layout, which is caused by repeated patterns having such a form that teeth fall out; therefore, in the sense amplifier DSAb, only the pattern of the sense amplifier is generally arranged. This is because an increase in area is caused if the memory cells are connected thereto and the sense amplifier is operated in the same manner as the others.
In the case where, in write operation by the aforementioned prior art, the write amplifier WA drives the pair of the data path lines DB/DBB, and then row addressee signals YS0-YSm are selected so that the data path lines DB/DBB are connected to the bit lines which are objects of writing, the wiring capacitance of the pair of data path lines DB/DBB is generally far larger than that of the selected pairs of bit lines (BL0/BLB0)-(BLm/BLBm). Therefore, the sense amplifier can be easily inverted. However, in the case where the row address signals YS0-YSm are selected before the write amplifier WA drives the pair of data path lines DB/DBB, the pair of data path lines DB/DBB is being driven by the corresponding sense amplifiers SA0-SAm connected to the selected pairs of the bit lines (BL0/BLB0)-(BLm/BLBm). The write amplifier WA must invert the corresponding sense amplifiers SA0-SAm by only the ability of the write amplifier WA itself.
The example of 4 column-block write operation will be described below, referring to the block view of FIG. 1 and the operation timing view of FIG. 3. When row address signals YSm-3, YSm-2, YSm-1 and YSm for the 4 columns are firstly selected, the pair of data path lines DB/DBB is being driven by the 4 sense amplifiers SAm-3, SAm-2, SAm-1 and SAm. In the case where the information from the sense amplifiers SAm-3, SAm-2, SAm-1 and SAm is wholly the same and the write data are inverse data of the information, the 4 sense amplifiers SAm-3, SAm-2, SAm-1 and SAm must be inverted by the ability of the write amplifier WA itself.
At that time, the ability to invert the sense amplifiers SAm-3, SAm-2, SAm-1 and SAm by the write amplifier WA becomes lower because the wiring resistance of the pair of data path lines DB/DBB is higher, as the memory cells MC which are object of writing are more distant from the write amplifier. Thus, rewriting speed becomes slower and operation at low voltage becomes worse.
In recent years, the material for wiring has been changed from aluminum to tungsten because of easiness of minute processing, and consequently wiring resistivity has been about 3 times as high as prior art. Furthermore, the capacity of a memory has become larger to increase the number of memory cells into which writing is carried out at a time by block write function.
In the light of the above, in order to carry out high speed writing, it is essential to make the size of the transistor constituting the write amplifier WA larger or to divide the write amplifier WA and shorten the wiring of the pair of data path lines DB/DBB so as to reduce wiring load. This results in obstructing high integration.